Instruction pipelines of processors are designed to process instructions in multiple pipeline stages, in successive clock cycles. To improve performance, some instructions may be executed out of program order in the instruction pipeline, wherein, instructions like branch instructions may be speculatively executed based on a prediction of their direction. If a branch instruction is predicted “taken,” control flow is transferred to a branch target address of the taken branch instruction and instructions are to be fetched and processed from the branch target address. If the branch instruction is predicted “not-taken,” then control flow does not change and instructions following the branch instructions are to be fetched and processed. In either case if the branch is incorrectly predicted (or mispredicted) as taken or not-taken, then instructions would have been fetched and executed down a wrong-path and these wrong-path instructions will be flushed or thrown away once the misprediction is realized several clock cycles after the branch was incorrectly predicted. Therefore, fetching and executing wrong-path instructions leads to unnecessary power consumption and utilization of resources of the processor.
A conventional approach to reducing power consumption associated with wrong-path instructions involves determining a number of speculatively executed branches that are still unresolved or in-flight in a processor pipeline. Based on this number (e.g., if it is above or below a specified threshold), decisions are made whether to throttle the fetching of new instructions. This approach is based on the notion that if a large number of branch instructions are unresolved, there is a higher likelihood that at least some of these branch instructions were mispredicted and therefore, at least some wrong-path instructions may be fetched and executed due to these likely mispredictions. Thus, according to this approach, fetching future instructions are stalled (or, as referred to herein, the pipeline is throttled) until the number of in-flight branch instructions in the pipeline decreases.
However, the above conventional approach suffers from the drawback that all in-flight branch instructions are essentially treated as having the same likelihood of being mispredicted. In practical applications, this assumption may be incorrect because the prediction accuracies may vary for different branch instructions. Therefore, the conventional approaches to pipeline throttling may hurt performance due to the inaccurate manner in which throttling is applied.
Accordingly, there is a need in the art to avoid the drawbacks of the above-described conventional approach and reducing wasteful power consumption associated with wrong-path instructions while minimizing any impact on performance.